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Hack a Day
While the “M” in MIDI stands for “musical”, it’s possible to use this standard for other things as well. [s-ol] has been working on a VJ setup (mixing video instead of music) using various potentiometer-based hardware and MIDI to interface everything together. After becoming frustrated with drift in the potentiometers, he set out to outfit the entire rig with custom-built encoders.
[s-ol] designed the rotary-encoder based boards around an FPGA. It monitors the encoder for changes, controls eight RGB LEDs per knob, and even does capacitive touch sensing on the aluminum knob itself. The FPGA communicates via SPI with an Arduino master controller which communicates to a PC using a serial interface. This is [s-ol]’s first time diving into an FPGA project and it looks like he hit it out of the park!.
Even if you’re not mixing video or music, these encoders might be useful to any project where a standard analog potentiometer isn’t accurate or precise enough, or if you just need something that can dial into a specific value quickly. Potentiometers fall short in many different ways, but if you don’t want to replace them you might modify potentiometers to suit your purposes.
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Hack a Day
Microcontrollers are a great way to learn about developing for embedded systems. However, once you outgrow their capabilities, FPGAs bring muscle that’s hard for even the fastest-clocked micros to match. If you’re doing anything with high-speed signals, loads of RAM, or something that requires lots of parallel calculation, you can’t go past FPGAs. Dev boards can be expensive, but there are alternatives. There’s a nifty project on Github trying to repurpose commodity hardware into a useful FPGA development platform.
Chubby75 is a project to reverse engineer the RV901T LED “Receiver Card”. This device is used to receive signals over Ethernet, and clock data out to large LED displays. This sort of work is highly processor intensive for microcontrollers, but a cinch for FPGAs to manage. The board packs a user-reprogrammable Spartan 6 FPGA, along with twin Gigabit Ethernet ports and 64MB of SDRAM. Thanks to the fact that its firmware is not locked down, it has the potential to be repurposed into all manner of other projects. The boards are available for under $30 USD, making them a prime target for thrifty hackers.
Thus far, the team have begun poring through the hardware documentation and are looking to develop a toolchain to allow the boards to be easily reprogrammed. With the right tools, these boards could be the next thing in cheap FPGAs, taking over when the Pano Logic thin clients become thin on the ground.
[Thanks to KAN for the tip!]
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Hack a Day
There’s something about Frequency Modulation (FM) synthesizer chips that appeals to a large audience. That’s one of the reasons behind [René Ceballos]’s XFM project, aiming to duplicate on an FPGA the sound of pure-FM synthesizer chips of the past such as the Yamaha DX series, OPL chip series and TX81Z/802/816. The result is a polyphonic, 32-voice, 6-operator FM synthesizer stereo module.
The project page goes into a lot of detail about the design choices which ultimately led to XFM being implemented on an FPGA, instead of using a dedicated DSP or MCU. Coming from the world of virtual synthesizers running on PCs, [René ]’s first impulse was to implement something on a Raspberry Pi or equivalent. Unfortunately these boards require a lot of power (ruling out battery-powered operation) and can hardly be called real-time, which led [René ] to abandon this attempt.
The design choice against the use of an MCU is simple: though capable of real-time processing, they lack the necessary power to make them a good choice for audio-processing. Working through the calculations to determine what kind of processing power would be needed, it was found that around 650 MIPS would be needed, a figure which most MCUs struggle to achieve a fraction of.
As one of the further requirements for XFM was that it should be as cheap as possible, this ruled out as too expensive the DSP chips which do have the power and hardware features needed. The component chosen was a Xilinx Spartan 6 FPGA, which though somewhat infamous and shunned in FPGA circles turns out to be a very economical option for this project.
Picking the Mojo V3 with the Spartan 6 XC6SLX9 that has 16 DSP blocks as platform, [René ] then created an add-on board for the MIDI and SPDIF interfaces, along with an EEPROM for program memory and a dual sigma-delta 16-bit DAC implemented using discrete components.
The result is pretty impressive as you can hear for yourself in the below included video, with a brief look at the XFM system in action as well.
Being a mostly open design, the design files and software are available via the website for anyone who wants to build their own XFM system, assuming they can use the bit file for the currently supported FPGA boards. Unfortunately the Mojo V3 board has been phased out at this point, but [René ] has indicated in a response to us that he has ported the HDL to the Numato Mimas and CMOD A7 boards and will make the bit files for those platforms available in a few weeks.
There is talk of perhaps doing a crowdfunding campaign for a custom board or even an ASIC version in the future, which is the reason for not open sourcing the HDL.
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Hack a Day
The Field Programmable Gate Array (FPGA) is one of the most exciting tools in the modern hacker’s arsenal. If you can master the FPGA, you can create hardware devices that not only morph and change based on your current needs, but can power through repetitive tasks at phenomenal rates. The only problem is, working with FPGAs can be a bit intimidating for newbies. One could argue that the technology is waiting on its “Arduino” moment; the introduction of a cheap development board coupled with easy to use software that brings FPGA hacking into the mainstream.
If everything goes according to plan, the wait might soon be over. [Ryan Jacobs] believes his project WebFPGA is the easiest and fastest way to get your hands dirty with this incredible technology. Outwardly the hardware could pass for an Arduino Nano clone, with a bunch of GPIO pins and a couple of LEDs on a small breadboard-friendly PCB. Certainly a no-frills presentation. It’s the software side is where things get interesting: all you need to develop for this FPGA is a modern web browser.
Currently Chrome, Opera, and Edge are supported, even if they’re running on relatively low-end computers. [Ryan] says this makes it much easier and cheaper to roll out FPGA classes in schools, as students can do everything with their existing Chromebooks. As the video after the break shows, you can even get away with using a sufficiently powerful smartphone to do some FPGA hacking on the go.
So what’s the trick? Essentially the heavy-lifting is done remotely: all of the synthesis is performed in their cloud backend, with the final bitstream delivered to the user for installation through WebUSB. If you’re more comfortable on the command line, [Ryan] says they’re currently working on tools which will allow you to perform all the necessary interactions with their cloud service without the browser.
The more critical Hackaday reader will likely be concerned about lock-in. What happens if you buy one of these development boards without a license for the service, or worse, what happens if WebFPGA goes belly-up down the road? To that end, [Ryan] makes it clear that their hardware is completely compatible with existing offline FPGA development tools such as the open source IceStorm.
We’ve seen considerable interest in low-cost FPGA development platforms, with readers perhaps recalling the excitement surrounding the fire sale of the Pano Logic thin clients. Despite efforts to make developing for these systems even easier, it’s hard to imagine the bar getting much lower than what WebFPGA is shooting for. Their Kickstarter campaign is close to crossing the finish line, and we’re very interested to see where the product goes from here.
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Hack a Day
When the only tool you have is a hammer, all problems look like nails. And if your goal is to emulate the behavior of an FPGA but your only tools are FPGAs, then your nail-and-hammer issue starts getting a little bit interesting. That’s at least what a group of students at Cornell recently found when learning about the Xilinx FPGA used by a researcher in the 1990s by programming its functionality into another FPGA.
Using outdated hardware to recreate a technical paper from decades ago might be possible, but an easier solution was simply to emulate the Xilinx in a more modern FPGA, the Cyclone V FPGA from Terasic. This allows much easier manipulation of I/O as well as reducing the hassle required to reprogram the device. Once all of that was set up, it was much simpler to perform the desired task originally set up in that 90s paper: using evolutionary algorithms to discriminate between different inputs.
While we will leave the investigation into the algorithms and the I/O used in this project as an academic exercise for the reader, this does serve as a good reminder that we don’t always have to have the exact hardware on hand to get the job done. Old computers can be duplicated on less expensive, more modern equipment, and of course video games from days of yore are a snap to play on other hardware now too.
Thanks to [Bruce Land] for the tip!
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Hack a Day
We will admit it: mostly when we see a homebrew CPU design on an FPGA, it is a simple design that wouldn’t raise any eyebrows in the 1970s or 1980s. Not so with [Henry Wong’s] design, though. His x86-like design does superscalar out-of-order execution, just like big commercial modern CPUs. Of course [Henry] designs CPU architectures for Intel, so that’s not surprising. You can see a very detailed talk on the design in the video, below. You can also read the entire thesis project.
[Henry] starts out with a description of FPGAs and soft processors. He also covers the use of multiple instruction issue to increase the virtual clock rate of a CPU. In other words, if a 100 MHz CPU can do one instruction at a time, it won’t be any faster — in theory — than a 50 MHz CPU that can do two instructions at once. Of course, trying to do two at once has some overhead, so that won’t be completely true.
Our first impression is that the x86 instruction set is relatively difficult to implement. But [Henry] makes the point that if you can provide a robust implementation — which could include emulation of some of the more difficult parts like floating point — you can run a wealth of software with no changes.
We were impressed with the method used to verify the design before it went to the FPGA using Bochs, a CPU simulator together with a known-good model of the x86. That’s especially helpful when you have to implement techniques like register renaming and a distributed matrix scheduler.
If you’ve never worked with a CPU design before, this might not be a good choice for getting your feet wet. But if you are ready to move from a toy CPU to something bigger, there’s a lot of good information in here. Need even more FPGA coaching? Try our boot camps. If you’d rather hack on RISC-V, we’ve looked at that, too.
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Hack a Day
Sometimes, rather than going the commercialistic route, it can be nice to make a gift for that personal touch. [Mahesh Venkitachalam] had been down this very road before, often stumbling over that common hurdle of getting in too deep and missing the deadline of the occasion entirely. Not eager to repeat the mistake, help was enlisted early, and the iCE bling earrings were born.
The earrings were a gift for [Mahesh]’s wife, and were made in collaboration with friends who helped out with the design. The earrings use a Lattice iCE40UP5k FPGA to control an 8×8 grid of SMD LEDs. This is all achieved without the use of shift registers, with the LEDs all being driven directly from GPIO pins. This led to several challenges, such as routing all the connections and delivering enough current to the LEDs. The final PCB is a 4-layer design, which made it much easier to get all the lines routed effectively. A buffer is used to avoid damaging the FPGA by running too many LEDs at once.
It’s a tidy build, which makes smart choices about component placement and PCB design to produce an attractive end result. LEDs naturally lend themselves to jewelry applications, and we’ve seen some great designs over the years. Video after the break.
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Hack a Day
Played against humans, Poker is a game as much about reading your opponent as it is about the cards you’re dealt. That doesn’t mean there aren’t certain mathematical ways to aid your decision making based on probabilities. In this vein, a group of students from Cornell’s ECE 5760 class built a pokerbot on an FPGA.
The bot uses the principle of Monte Carlo simulation to calculate the probabilities of an individual winning a hand of Limit Texas Hold’em. Calculating the entire set of possible hands is impractical, so in a Monte Carlo simulation a sample is calculated instead. By accelerating these calculations on an FPGA, the pokerbot is able to calculate 300,000 possible hands in just 150 ms, and present a probability of winning to the human player. This same calculation method is then used to make decisions for the computer players in the game, too.
The team report that the FPGA’s processing power brought a 10x speed up compared to their C++ program running on an Intel i7-6700HQ. The strong statistical calculations help to make the computer players engaging and realistic to play against.
It’s another great example of a project from Bruce Land’s classes, which are somewhat of a hotbed of development each year. Video after the break.
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Hack a Day
The MESM-6 project is focused on bringing the 1960s Soviet BESM-6 computer to the modern age of FPGAs and HDLs. At the moment the team behind this preservation effort consists out of [Evgeniy Khaluev], [Serge Vakulenko] and [Leo Broukhis], who are covering the efforts on the Russian-language project page.
The BESM-6 (in Russian: БЭСМ-6, ‘Bolshaya Elektronno-Schetnaya Mashina’ or ‘large electronic computing machine’) was a highly performing Soviet super computer that was first launched in 1968 and in production for the next 19 years. Its system clock ran at 9 MHz using an astounding number of discrete components, like 60,000 transistors and 170,000 diodes, capable of addressing 192 kB of memory in total. Of the 355 built, a few survive to this day, with one on display at the London Science Museum (pictured above). Many more images and information can be found on its Russian Wikipedia page.
For those not gifted with knowledge of the Russian language, the machine-translated summary reveals that the project goal is to make a softcore in SystemVerilog that is compatible with user mode BESM-6, using the same Pascal compiler as originally used with that system. Further goals include at least 24 kB of data memory, 96 kB of command memory and the addition of modern peripherals such as SPI and I2C.
The system is meant to be integrated with the Arduino IDE, using the Pascal compiler to make it highly accessible to anyone with an interest in programming a system like this. Considering the MIT license for the project, one could conceivably use a bit of Soviet-era computing might in one’s future FPGA efforts.
If after watching the BESM-6 video — included below — you feel inspired to start your own Soviet-computing project, we’d like to wish you luck the Russian way: Ни пуха ни пера!
Прохождение теста БЭСМ-6 (запись от 2008 года). https://t.co/SVF1HEVUoF pic.twitter.com/ZY4cDDmC8T
— x86128 (@x86128) April 18, 2018
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Hack a Day
Usually when writing emulation software for a system like the Game Boy, one makes sure to take as many shortcuts as possible in order to reduce the resources required for the emulation. This has however the unfortunate side-effect that it reduces the overall accuracy of the emulation and with it the compatibility with games on the system.
This is the basic reasoning behind projects which seek to abandon simplistic abstractions in favor of cycle-accurate, full compatibility approaches, of which MetroBoy is probably the most extreme one. Instead of abstracting away the hardware, it instead does the emulation at the circuit level. As with such other projects, this means that the emulator requires a lot more CPU cycles to get things just right. On the bright side, one can likely still run this emulator on any modern system.
As the MetroBoy author explains, he implemented code in C++ which allowed him to construct circuits in an HDL-style manner, which should theoretically also allow him to generate a Verilog (or VHDL) softcore out of the project. As a demonstration of implementing HDL in C++ it’s decidedly interesting.
An approach like this is pretty much the exact opposite of a project like the UltraHLE (ultra high-level emulator) Nintendo 64 emulator, which used the knowledge that Nintendo 64 games are written in C as a first step to creating libraries that the code in the Nintendo 64 ROMs would call instead of the native (Nintendo) libraries. This allowed N64 games to directly run on the target system, with the graphic and system calls translated by UltraHLE into native OS calls, using the 3dfx Glide API for accelerated graphics.
While an approach like UltraHLE took allows for the most minimal use of system resources by essentially foregoing emulation completely, for retro systems like the Game Boy where games were implemented in assembly on bare hardware, using this circuit-level emulation ensures that one gets the most accurate match with the original handheld console experience.
As a word of caution to those who are now itching to try out MetroBoy, its Github site notes that it currently lacks support for game saves, uses a mixture of original Game Boy (DMG) and Game Boy Advance SP (AGS) hardware that confuses some games and has rather buggy sound support.
If playing around with software-defined Game Boy circuits isn’t enough and would like to literally look inside a real Game Boy, the X-ray image from the top of the article is something Chris over at Elektronaut pulled off several years ago.
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Hack a Day
When Pano Logic went out of business in 2012, their line of unique FPGA-based thin clients suddenly became a burden that IT departments didn’t want anything to do with. New and used units flooded the second-hand market, and for a while you could pick these interesting gadgets up for not much more than the cost of shipping. Thanks to considerable interest from the hacking community the prices for these boxes have climbed a bit on eBay, but they’re still a great way to get your feet wet with FPGA hacking.
Especially now, as Pano Logic fanatic [Skip Hansen] has figured out how to flash a new firmware on them without having to crack open the case and break out the JTAG or SPI programmer. For the seasoned hardware hacker that might not seem like a big deal, but if you’re new to the game or just more interested in the software side of the equation, this trick makes things considerably more accessible. Having an external programmer is still a good idea if things go south, but if you’re just looking to flash some demos and see what the hardware is capable of this is a huge quality of life improvement.
Even if you aren’t interested in fiddling with the orphaned products of a defunct Bay Area startup, the write-up is a fascinating look at practical software reverse engineering. As it turns out, [Skip] didn’t create this new firmware update tool from scratch. He actually opened up the official Linux update utility from Pano Logic in Ghidra and was able to figure out where the firmware image actually lived inside the program. He then wrote his own tool in C which will patch the update tool with a user-supplied firmware image.
After patching, all you need to do is follow the official update procedure, which Pano Logic helpfully documented in the YouTube video after the break. [Skip] mentions he didn’t find any clear license information in the official software he was fiddling with, and of course with the company out of business it’s not too likely anyone is going to come knocking down his door anyway. Still, he says the downloads for the Pano Logic updater are still floating around on the tubes out there for you to find, so he’s not distributing anyone’s code but his own in this project.
There are a number of hackers out there working to turn the Pano Logic thin clients into useful general purpose FPGA platforms, such as [Tom Verbeure], who’s incredible graphics demos got [Skip] inspired to grab his own unit off eBay. With support for USB and SDRAM added by [Wenting Zhang] while getting his FPGA GBA emulator running on the hardware, it seems there’s never been a better time to get on the Pano Logic train.
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Hack a Day
With the wide availability of Raspberry Pi hardware and pre-baked Linux distros with emulators ready to go, making a retro handheld is easier than ever. Emulation isn’t the only way to go about playing old games however. [Wenting Zhang] decided to instead recreate the Nintendo Game Boy in Verilog, and …read more
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Hack a Day
If you’re reading this article on a desktop or laptop computer, you’re probably staring at millions of pixels on a TFT LCD display. TFT became a dominant technology due to its picture quality and fast response times, but it’s not the only way to build an LCD. There are cheaper …read more
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Hack a Day
FPGAs are wonderful things, packed with logic cells that can be reconfigured as your heart desires. They excel at signal processing, anything requiring speed, and recreating vintage hardware. In that vein, [Jon Thomasson] decided to bring back the original Nintendo Entertainment System, in perfboard form.
The build uses a Spartan …read more
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Hack a Day
When you think of analog computing, it’s possible you don’t typically think of FPGAs. Sure, a few FPGAs will have specialized analog blocks, but usually they are digital devices. [Bruce Land] — a name well-known to Hackaday — has a post about building a digital differential analyzer using an FPGA and it is essentially an analog computer simulated on the digital fabric of an FPGA.
Whereas traditional analog computers use operational amplifiers to do mathematical integration, on the FPGA [Land] uses digital summers The devices simulate a system of differential equations, which can be nonlinear.
Of course, at heart it …read more
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Hack a Day
If you want to talk about RISC-V, the Open Source instruction set for CPUs, you’re probably talking about microcontrollers. You can buy small but powerful RISC-V micros on par with an ARM Cortex-M4 right now. Deep in the pipeline are cores for something resembling SoCs, the kind you’d find in desktop NAS solutions, maybe a few routers, and smart TVs. This is great and all, but our idea of a ‘computer’ is still a desktop. When is the Open instruction set desktop coming? Well, it’s here right now. [Andrew Back] built a RISC-V desktop computer. It runs Linux, it comes …read more
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Hack a Day
We really love when hacks of previous hacks show up in the tip line. It shows how the hardware hacking community can be a feedback loop, where one hack begets the next, and so on until great things are everywhere. This hacked joystick port for an FPGA Pac Man game is a perfect example of that creative churn.
The story starts with Pano Man, a version of the venerable arcade game ported to a Pano Logic FPGA thin client by [Skip]. We covered that story when it first came out, and it caught the attention of [Tom Verbeure], particularly …read more
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Hack a Day
Glowing and blinking things are some of our favourite projects around these parts, and the bigger, the better. [Thomas] wrote to us recently to share the design and construction of a large LED wall at the Oregon Museum of Science, and the results are nothing short of impressive.
The concept involved a large LED wall that would be completely hidden when switched off. The team decided to approach this by hiding high-brightness LED panels using APA102 strings behind milky-white plexiglass panels covered with a woodgrain print. The screen has a total of 90,000 pixels, arranged in a 408×220 resolution display. …read more
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Hack a Day
We are somewhat spoiled because electronics today are very reliable compared to even a few decades ago. Most modern electronics obey the bathtub curve. If they don’t fail right away, they won’t fail for a very long time, in all likelihood. However, there are a few cases where that’s not a good enough answer. One is when something really important is at stake — the control systems of an airplane, for example. The other is when you are in an environment that might cause failures. In those cases — near a nuclear reactor or space, for example, you often are …read more
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Hack a Day
The hackers over at Radiona.org, a Zagreb Makerspace, have been hard at work designing the ULX3S, an open-source development board for LATTICE ECP5 FPGAs. This board might help make 2019 the Year of the Hacker FPGA, whose occurrence has been predicted once again after not quite materializing in 2018. Even a quick look at the board and the open-source development surrounding it hints that this time might be different.
The ULX3S was developed primarily as an educational tool for undergraduate-level digital logic classes. As such, it falls into the “kitchen sink” category of FPGA boards, which include a comprehensive suite …read more
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Hack a Day
If you’ve been reading Hackaday for a while now, you might recall the tale of Pano Logic that we first covered all the way back in 2013. They were a company that put out some very interesting FPGA-based thin clients, but as occasionally happens in situations like this, the market wasn’t ready and the company went belly up. These thin clients, now without official support, invariably got dumped onto the second-hand market. Shame for Pano Logic and their staff, but good news for hackers like [Skip Hansen].
After seeing a few posts about the Pano Logic devices and general FPGA …read more
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Hack a Day
Classic battles: PC vs Mac, Emacs vs Vi, Tastes Great vs Less Filling, and certainly one that we debate around the Hackaday watercooler: command line or IDE? There’s something to be said for using good old command line tools, and even if you like to configure your favorite editor to be nearly an IDE, at least it is one you are familiar with and presumably leverage over several different uses.
Most commercial FPGA tools come with a heavy-weight IDE. The open source tools for Lattice (IceStorm) typically is driven by the command line or a makefile. Until now. [Rochus-Keller] released …read more
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Hack a Day
If you have a thing for old game development — things like the Atari 2600 or similar period arcade games — you might already know about the 8bitworkshop IDE. There you can develop code in your browser for those platforms. In a recent blog post, the site announced you can now also do FPGA development in the IDE.
According to the site:
Most computers are fast enough to render a game at 60 Hz, which requires simulating Verilog at almost 5 million ticks per second.
To activate Verilog, you need to select the hamburger menu to the top left, select …read more
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Hack a Day
If you’ve ever wanted to sit at the console of the machine that started the revolution in interactive computing, your options are extremely limited. Of the 53 PDP-1 machines that Digital Equipment Corporation made, only three are known to still exist, and just one machine is still in working order at the Computer History Museum. So a rousing game of Spacewar! on the original hardware is probably not something to put on your bucket list.
But thanks to [Hrvoje], there’s now an FPGA emulation of the PDP-1 that lets you play the granddaddy of all video games without breaking into …read more
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Hack a Day
[Kenneth Wilke] is undertaking a noble quest – to build a homebrew microcomputer, based around the venerable 6502. As a prelude to this, he set out to interface the hallowed CPU to an FPGA, and shared the process involved.
[Kenneth] is using an Arty A7 FPGA development board which is a great fit for purpose, having plenty of I/O pins and being relatively easy to work with for the home tinkerer. This is an important consideration, as many industrial strength FPGAs require software licences to use which can easily stretch into the tens of thousands of dollars.
The 6502 is …read more
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Hack a Day
The Game Genie is a classic of the early 90s video game scene. It’s how you would have beaten the Ninja Turtles game, and it’s why the connector in your NES doesn’t work as it should. They never made a Game Genie for the Atari 2600, though, because by the time the Game Genie was released, the Atari was languishing on the bottom shelves of Toys R Us. Now though, we have FPGAs and development tools. We can build our own. That’s exactly what [Andy] did, and his Game Genie for the 2600 works as well as any commercial product …read more
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Hack a Day
Over on GitHub, [ttsiodras] wanted to learn VHDL. So he started with an algorithm to do Mandelbrot sets and moved it to an FPGA. Because of the speed, he was able to accomplish real-time zooming. You can see a video of the results, below.
The FPGA board is a ZestSC1 that has a relatively old Xilinx Spartan 3 chip onboard. Still, it is plenty powerful enough for a task like this.
The project doesn’t directly drive a display. It does the math, stores the results in the board’s onboard RAM and then sends a frame to the PC using the …read more
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Hack a Day
If you want to use FPGAs, you’ll almost always use an HDL like Verilog or VHDL. These are layers of abstraction just like using, say, a C compiler is to machine language or assembly code. There are other challengers to the throne such as SpinalHDL which have small but enthusiastic followings. [Tom] has a post about how the VexRISC-V CPU leverages SpinalHDL to make an extremely flexible system that is as efficient as plain Verilog. He says the example really shows off why you should be using SpinaHDL.
Like a conventional programming language, it is easy to find niche languages …read more
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Hack a Day
A few years back, a company by the name of Pano Logic launched a line of FPGA-based thin clients. Sadly, the market didn’t eventuate, and the majority of this stock ended up on eBay, to eventually be snapped up by eager hackers. [Tom] is one of those very hackers, and decided to try some raytracing experiments with the hardware.
[Tom] has one of the earlier Pano Logic clients, with VGA output and a Xilinx Spartan-3E 1600 FPGA under the hood. Due to limited RAM in the FPGA, and wanting to avoid coding a custom DRAM controller for the memory on …read more
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Hack a Day
While desktop computers have tons of computing power and storage, some small CPUs don’t have a lot of space to store things. What’s more is some CPUs don’t do multiplication and division very well. Same can be said for FPGAs. So suppose we are going to grab a bunch of three-digit decimal numbers from, say, a serial port. We want to store as many as we can, and we don’t want to do a lot of math because we can’t, it is slow, or perhaps it keeps our processor awake longer and we want to sleep to conserve power. We …read more
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Hack a Day
[Adam Taylor] always has interesting FPGA posts and his latest is no exception. He wanted to use a Zynq for image processing. Makes sense. You can do the high-speed parallel parts in the FPGA fabric and do higher-level processing on the built-in CPU. The problem is, of course, you need to get the video data into the system. [Adam] elected to use the Mobile Industry Processor Interface (MIPI) Camera Serial Interface Issue 2 (CSI-2).
This high-speed serial interface is optimized for data flowing in one direction. The camera, or the master, sends a number of bits (at least one) serially …read more
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Hack a Day
One of the ways people use FPGAs is to have part of the FPGA fabric hold a CPU. That makes sense because CPUs are good at some jobs that are hard to do with an FPGA, and vice versa. Now that the RISC-V architecture is available it makes sense that it can be used as an FPGA-based CPU. [Clifford Wolf] created PicoSOC — a RISC-V CPU made to work as a SOC or System on Chip with a Lattice 8K evaluation board. [Mattvenn] ported that over to a TinyFPGA board that also contains a Lattice FPGA and shows an example …read more
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Hack a Day
It’s the 21st century, and according to a lot of sci-fi movies we should have perfected AI by now, right? Well we are getting there, and this project from a group of Cornell University students titled, “FPGA kNN Recognition” is a graceful attempt at facial recognition.
For the uninitiated, the K-nearest neighbors or kNN Algorithm is a very simple classification algorithm that uses similarities between given sets of data and a data point being examined to predict where the said data point belongs. In this project, the authors use a camera to take an image and then save its histogram …read more
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Hack a Day
You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your FPGA of choice and see if it works. If it does, that was a great idea. If it doesn’t, it was a terrible idea because — typically — it is hard to look inside the FPGA. That’s why you’ll typical simulate your logic on a desktop computer before you commit it to the FPGA. But that means you have to delay gratification long enough to …read more
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Hack a Day
Last time I talked about how I took the open source Verifla logic analyzer and modified it to have some extra features. As promised, this time I want to show it in action, so you can incorporate it into your own designs. The original code didn’t actually capture your data. Instead, it created a Verilog simulation that would produce identical outputs to your FPGA. If you were trying to do some black box simulation, that probably makes sense. I just wanted to view data, so I created a simple C program that generates a VCD file you can read with …read more
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Hack a Day
Ok, we’ll admit it. We like FPGAs because it reminds us of wiring up a 100-in-1 kit when we were kids. But the truth is, many projects are just as well off to have a CPU. But there’s a real sweet spot when you have a CPU and an FPGA together. Intel (or Altera, if you prefer) has the NIOS II CPU core, but that’s hard to configure, right? Maybe not, thanks to a project by [jefflieu] over on GitHub. He’s assembled some basic definitions and libraries to easily — relatively speaking — use NIOS II on the MAX1000 as …read more
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Hack a Day
In a surprising move, ARM has made two Cortex-M cores available for FPGA development at no cost.
In the over three decades since [Sophie Wilson] created the first ARM processor design for the Acorn Archimedes home computer, the architecture has been managed commercially such that it has become one of the most widely adopted on the planet. From tiny embedded microcontrollers in domestic appliances to super-powerful 64-bit multi-core behemoths in high-end mobile phones, it’s certain you’ll own quite a few ARM processors even if you don’t realise it. Yet none of those processors will have been made by ARM, instead …read more
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Hack a Day
We’ve done a lot of posts on how to use the Lattice iCEstick ranging from FPGA tutorials to how to use one as a logic analyzer. If you picked up one of these inexpensive boards here’s a fun little experiment. [T4D10N] saw a project [Hamster] put together to send SOS on the FM radio band using nothing but an FPGA. [Hamster used a Spartan], so he decided to do the same trick using an iCEstick with the open source IceStorm tools.
You might be surprised that the whole thing only takes 53 lines of Verilog — less if you cut …read more
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Hack a Day
How do you preserve high scores in an old arcade cabinet when disconnecting the power? Is it possible to inject new high scores into a pinball machine? It was the b-plot of an episode of Seinfield, so it has to be worth doing, leading [matthew venn] down the rabbit hole of FPGAs and memory maps to create new high scores in a pinball machine.
The machine in question for this experiment is Doctor Who from Williams, which, despite being a Doctor Who pinball machine isn’t that great of a machine. Still, daleks. This machine is powered by a Motorola …read more
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Hack a Day
It is no secret that we like the Lattice iCE40 FPGA. It has a cheap development board and an open source toolchain, so it is an easy way to get started developing low-cost, low-power FPGA designs. There are a few members of the family that have similar characteristics including the top-of-the-line UltraPlus. [Steve] from Lattice and [Michael Klopfer] from the University of California Irvine have a three-part video series that explain the architecture of the devices. Altogether, the videos are about an hour long and — of course — they use the official tools, not IceStorm. But it is still …read more
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Hack a Day
We are big fans of tools in the browser for education. You have a consistent environment maintained by someone else, you don’t have to install anything, and you can work from any computer you happen to find yourself. The HDLBits site has a great set of Verilog “exams” that would be a big help to anyone trying to learn or brush up on their Verilog skills.
The site offers a range of topics that go from the silly (output a constant 1 or 0) to full-blown state machines and testbenches. The site isn’t tutorial in nature, instead it offers a …read more
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Hack a Day
If you’re headed over to mainland China as a tourist, it’s possible to get to most of the country by rail. China is huge though, about the same size as the United States and more than twice the size of the European Union. Traveling that much area isn’t particularly easy. There are over 300 train terminals in China, and finding the quickest route somewhere is not obvious at all. This is an engineering challenge waiting to be solve, and luckily some of the students at Cornell Engineering have taken a stab at efficiently navigating China’s rail system using an FPGA. …read more
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Hack a Day
FLIR are making some really great miniature thermal cameras these days, designed for applications such as self-driving cars, and tools that help keep firefighters safe. That’s great and all, but these thermal cameras are so cool, you really just want to play with one. That’s what [greg] was thinking when he designed a PCB backpack that captures thermal images from a FLIR Boson and stores it on an SD card. It’s a thermal action cam, and an impressive bit of FPGA development, too.
The FLIR product in question is a Boson 640, an impressive little camera that records in 640×512 …read more
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Hack a Day
We are always excited when we see [Hamster] post an FPGA project, because it is usually something good. His latest post doesn’t disappoint and shows how he uses the CORDIC algorithm to generate very precise sine and cosine waves in VHDL. CORDIC (Coordinate Rotation Digital Computer; sometimes known as Volder’s algorithm) is a standard way to compute hyperbolic and trigonometric functions. What’s nice is that the algorithm only requires addition, subtraction, bit shifts, and a lookup table with an entry for each bit of precision you want. Of course, if you have addition and negative numbers, you already have subtraction. …read more
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Hack a Day
Being able to communicate between a host computer and a project is often a key requirement, and for FPGA projects that is easily done by adding a submodule like a UART. A Universal Asynchronous Receiver-Transmitter is the hardware that facilitates communications with a serial port, so you can send commands from a computer and get messages in return.
Last week I wrote about an example POV project that’s a good example for learn. It was both non-trivial and used the board’s features nicely. But it has the message hard coded into the Verilog which means you need to rebuild the …read more
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Hack a Day
You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some printed information or you might get a graphical result by dumping a waveform, but you don’t usually see the circuit. A new site combines Yosys and a Javascript-based logic simulator to let you visualize and simulate Verilog in your browser. It is a work in progress on GitHub, so you might find a few hiccups like we did, but it is still an …read more
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Hack a Day
Everybody wants to give FPGA development a try and here’s a great way to get into it. You can build your own Persistence of Vision display using a $30 dev board. It’s a fun project, and you’ll learn quite a bit about designing for an FPGA, as well as using the Quartus design software.
The inspiration for this article comes from [vpecanins] who did an example project where you wave the board back and forth and a message appears in mid air. This uses the MAX1000, a pretty powerful yet odd FPGA board for about $30. It contains an Intel …read more
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Hack a Day
There’s never been a better time to get into using FPGAs. Nearly all vendors have some level of free software and while boards haven’t gotten as cheap as ones with microcontrollers, the prices are way down. [Joel Williams] was frustrated when his board of choice became unavailable, so he decided to compile data on as many cheap boards as he could.
[Joel] covers the major vendors like Intel and Altera. But he also includes information on Actel, Cypress, and Lattice. While the list probably isn’t comprehensive, it is a lot of information about many popular boards. The notes are helpful …read more
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Hack a Day
A rite of passage for a digital designer is to build a CPU. That may seem a formidable task and if you are thinking of building a modern CPU like the one in your PC, it is. However, a simple CPU is well within the reach of anyone who can sling some logic gates or HDL. We’ve even seen CPUs built in Minecraft. Now you can play nandgame and build a CPU step-by-step in your browser.
The game is based on the popular From NAND to Tetris site. True to the name you start out with a single NAND gate …read more
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Hack a Day
Although there are a few exceptions, FPGAs are predominantly digital devices. However, many FPGA applications process analog data, so you often see an FPGA surrounded by analog and digital converters. This is so common that Opal Kelly — a producer of FPGA tools — launched the SYZYGY open standard for interconnecting devices like that. [Armeen] — a summer intern at Opal Kelly — did a very interesting open source FPGA-based signal generator using a Xilinx FPGA, and a SYZYGY-compliant digital to analog converter.
As you might expect, [Armeen] used a lot of Opal Kelly hardware and software in the project. …read more
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Hack a Day
FPGAs have gone from being a niche product for people with big budgets to something that every electronics experimenter ought to have in their toolbox. I am always surprised at how many people I meet who tell me they are interested in using FPGAs but they haven’t started. If you’ve been looking for an easy way to get started with FPGAs, Hackaday’s FPGA boot camp is for you. There’s even a Hackaday.io chat in the group specifically for FPGA talk for questions and general discussion!
While it is true FPGAs aren’t for everything, when you need them you really need …read more
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Hack a Day
There has to be more than one of us who over the years since the launch of systems like the original Game Boy have eyed up these handheld platforms and thought “You could make a really neat little oscilloscope with that!” But the commercial systems are closed-source, locked down, and proprietary, so in many cases there’s little easy prospect of such a device being created.
Fortunately though, there are now very accessible handheld gaming platforms, and [James Bowman], the creator of the Gameduino series of boards, writes in to tell us about an oscilloscope project for the Gameduino 3 created …read more
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Hack a Day
The Mandelbrot Set is a mathematical oddity where a simple function creates an infinitely complex landscape that you can literally zoom into forever. Like most people, I’ve downloaded Mandelbrot set viewers and marveled at the infinite whorls and spirals, and then waited while each frame took minutes or hours to render as I zoomed in. [Michael Henning], [Max Rademacher] and [Jonathan Plattner] decided to throw some modern computational muscle at this problem by building an interactive Mandelbrot set viewer using a laptop and two FPGA boards.
The three are students at Cornell, and this was their final project for the …read more
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Hack a Day
Got $4,000 to spend? Even if you don’t, keep reading — especially if you develop with FPGAs. Exostiv’s FPGA debugging setup costs around $4K although if you are in need of debugging a complex FPGA design and your time has any value, that might not be very expensive. Then again, most of us have a lot of trouble justifying a $4,000 piece of test gear. But we wanted to think about what Exostiv is doing and why we don’t see more of it. Traditionally, debugging FPGAs meant using JTAG and possibly some custom blocks that act like a logic analyzer …read more
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Hack a Day
After the Norman invasion of England, William the Conqueror ordered a great reckoning of all the lands and assets owned. Tax assessors went out into the country, counted sheep and chickens, and compiled everything into one great tome. This was the Domesday Book, an accounting of everything owned in England nearly 1000 years ago. It is a vital source for historians and economists, and one of the most important texts of the Middle Ages.
In the early 1980s, the BBC set upon a new Domesday Project. Over one million people took part in compiling writings on history, geography, and social …read more
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Hack a Day
When [Lawrence] showed us the Alice4 after Maker Faire Bay Area last weekend it wasn’t apparent how special the system was. The case is clean and white, adorned only with a big red button below a 7″ screen with a power switch around the back. When the switch is flicked the system boots to display a familiar animation and drops you at a menu. Poking around from here elicits a variety of self-contained graphics demos, some interactive. So this is a Raspberry Pi in a box playing videos, right? Not even close.
Often retro computing focuses on personal computer systems. …read more
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Hack a Day
One of the best features of using FPGAs for a design is the inherent parallelism. Sure, you can write software to take advantage of multiple CPUs. But with an FPGA you can enjoy massive parallelism since all the pieces are just hardware. Every light switch in your house operates in parallel with the others. There’s a new edition of a book, titled Parallel Programming for FPGAs that explores that topic in depth and it is under the Creative Commons license. In particular, the book focuses on using Vivado HLS instead of the more traditional Verilog or VHDL.
HLS allows a …read more
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Hack a Day
Computers are great at a lot of things. However, general-purpose computers can benefit from help on certain tasks, which is why your video card and sound card both have their own specialized hardware to offload the CPU. If Accelize has its way, some of your hardware acceleration will be done in the cloud. Yes, we know. The cloud is the buzzword of the week and we are tired of hearing about it, too. However, this service is a particularly interesting way to add FPGA power to just about any network-connected CPU.
Currently, there are only four accelerators available, including a …read more
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Hack a Day
Today, Apple is known for iPhones, iPads, and a commitment to graphical user interfaces. But that wasn’t how it all started. The original Apple was a single board computer built around a 6502. In 1976, you could snag one for $666.66, but you needed to supply your own TV, power supply, and keyboard. [Alangarf] didn’t have an Apple 1, but he did have a 6502 CPU core for FPGAs from [Andrew Holme] that he fleshed out to an Apple I clone with a VGA output and PS/2 keyboard port. The project works with either an iCE40 board or a Terasic …read more
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Hack a Day
Have you ever found yourself in the need of a nine channel scope, when all you had was an FPGA evaluation board? Do not despair, [Miguel Angel] has you covered. While trying to make sense of the inner workings of a RAM controller core, he realized that he needed to capture a lot of signals in parallel and whipped up this 9-channel digital oscilloscope.
The scope is remote-controlled via a JavaScript application, and over Ethernet. Graphical output is provided as a VGA signal at full HD, so it is easy to see what is going on. Downloading sampled data to …read more
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Hack a Day
The Icoboard is a plug-in for the Raspberry Pi with a Lattice iCE FPGA onboard. Combined with a cheap A/D converter, [OpenTechLab] build a software-defined radio using all open source tools. He found some inexpensive converters that cost about $25 and were fast enough (32 MHz) for the purpose at hand. The boards also had a digital to analog converter and he was able to find the data sheets. You can see a video with the whole project covered, below.
The video, by the way, is pretty extensive (about an hour’s worth) and covers the creation of a PC board …read more
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Hack a Day
If you think of a medical x-ray, it is likely that you are imagining a photographic plate as its imaging device. Clipped to your tooth by your dentist perhaps, or one of the infamous pictures of the hands of [Thomas Edison]’s assistant [Clarence Madison Dally].
As with the rest of photography, the science of x-ray imaging has benefited from digital technology, and it is now well established that your hospital x-ray is likely to be captured by an electronic imaging device. Indeed these have now been in use for so long that their first generation can even be bought by …read more
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Hack a Day
[Bunnie Huang], creator of the Chumby and artisan of chips and electrons, is building his own completely open source laptop. It’s called the Novena, and is powered by a quad-core ARM CPU, it’s got enough bells and whistles to make any hacker happy including an on-board FPGA, dual Ethernet ports, and enough GPIO pins [...]
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Hack a Day
Regular Hackaday readers will be familiar with all the cool things you can do with FPGAs; emulating old video game consoles, cracking encryption protocols, and DIY logic analyzers become relatively simple projects with even a modest FPGA dev board on your workbench. Many FPGA boards aren’t geared towards prototyping, though, and breadboard friendly devices are [...]
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Hack a Day
For this year’s 7400 logic competition, [Nick] decided to build an FPGA out of logic chips. Perhaps a short explanation is in order to fully appreciate [Nick]‘s work. The basic component of an FPGA is a slice, or cell, that performs boolean operations on its input and sends the result on its output. The core of these slices [...]
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Hack a Day
We love to see derivative works that take a great hack and make it even better. This LCD Laptop resurrection project is an excellent example. [Alex] took the work seen on this other FPGA LCD driver and delivered a leap forward on the final hardware packaging. The link at the top drops you into the second page of [Alex's] [...]
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Hack a Day
We’ve seen FPGAs used to recreate everything from classic arcade games to ancient computers, but with each of these builds a common problem arises. Once you’ve got the hardware emulated on an FPGA, you’ve also got to get the ROMs into the project as well. In a very interesting hack, [Mike] figured out that the [...]
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Hack a Day
For those that grabbed one of these TM1638 UI boards you can now easily use it with your Stellaris Launchpad. [Dan O] took it upon himself to publish an ARM library for the UI board. There’s not a lot of new stuff to talk about here. We’ve already seen this being driven by an FPGA. [...]
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SecDocs
Authors:
David Hulton Tags:
FPGA Event:
Chaos Communication Congress 21th (21C3) 2004 Abstract: FPGAs (Field Programmable Gate Arrays) are slowly becoming more and more advanced and practical as high-speed computing platforms. In this talk, David will provide an in-depth introduction into the guts and capabilities of modern day FPGAs and show how you can take your current algorithms and efficiently convert them to gate logic and run them on hardware. This presentation will also introduce a set of open source cores (jawn v1.0) that will implement the basic functionality of john the ripper on FPGAs and allow you to crack password hashes as fast as 100+ PCs using FPGA PCMCIA cards on your laptop. Have you ever written an algorithm or a crypto cracker and wondered how fast it would run if you implemented it in hardware circuits with your bits flowing as fast as the electrons can move? What if you could put all of your algorithm's logic onto a specialized processor that does all of the work internally and just spits out an answer when it's done? It isn't as difficult as you think, and the chips are only getting faster and faster. FPGAs have many unique properties that can be exploited by a wide range of algorithms. This talk will release a new tool (jawn) that implements the basic functionality of john the ripper in FPGA logic. Jawn v1.0 currently implements DES, MD5, and Blowfish hash password cracking and runs on the ROAG platform, a Type 2 PCMCIA card with a XILINX Virtex-II Pro FPGA and a fully embedded PowerPC with 128MB RAM, 32MB Flash ROM, Ethernet, Serial Ports, and CANBus. It supports simple distributed processing by setting how many bits of the keyspace you want to search and allows you to search for just alpha numeric, all typeable/printable characters, or the full keyspace. Future plans are to run the key generation on the PowerPC for intelligent password generation. David will also go in-depth with new revolutionary approaches to FPGA programming including evolving algorithms / hardware / and other neural network concepts that become practical when using reprogrammable hardware. This presentation will provide a full introduction to how FPGAs work, different applications how to design logic for them, how to interface with your different peripherals, and how to optimize your design to be as size and speed efficient as possible. The goal is for the audience will walk out of the room with all the fundamentals needed to start doing FPGA development.
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9:59
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SecDocs
Authors:
David Hulton Tags:
FPGA Event:
Chaos Communication Congress 21th (21C3) 2004 Abstract: FPGAs (Field Programmable Gate Arrays) are slowly becoming more and more advanced and practical as high-speed computing platforms. In this talk, David will provide an in-depth introduction into the guts and capabilities of modern day FPGAs and show how you can take your current algorithms and efficiently convert them to gate logic and run them on hardware. This presentation will also introduce a set of open source cores (jawn v1.0) that will implement the basic functionality of john the ripper on FPGAs and allow you to crack password hashes as fast as 100+ PCs using FPGA PCMCIA cards on your laptop. Have you ever written an algorithm or a crypto cracker and wondered how fast it would run if you implemented it in hardware circuits with your bits flowing as fast as the electrons can move? What if you could put all of your algorithm's logic onto a specialized processor that does all of the work internally and just spits out an answer when it's done? It isn't as difficult as you think, and the chips are only getting faster and faster. FPGAs have many unique properties that can be exploited by a wide range of algorithms. This talk will release a new tool (jawn) that implements the basic functionality of john the ripper in FPGA logic. Jawn v1.0 currently implements DES, MD5, and Blowfish hash password cracking and runs on the ROAG platform, a Type 2 PCMCIA card with a XILINX Virtex-II Pro FPGA and a fully embedded PowerPC with 128MB RAM, 32MB Flash ROM, Ethernet, Serial Ports, and CANBus. It supports simple distributed processing by setting how many bits of the keyspace you want to search and allows you to search for just alpha numeric, all typeable/printable characters, or the full keyspace. Future plans are to run the key generation on the PowerPC for intelligent password generation. David will also go in-depth with new revolutionary approaches to FPGA programming including evolving algorithms / hardware / and other neural network concepts that become practical when using reprogrammable hardware. This presentation will provide a full introduction to how FPGAs work, different applications how to design logic for them, how to interface with your different peripherals, and how to optimize your design to be as size and speed efficient as possible. The goal is for the audience will walk out of the room with all the fundamentals needed to start doing FPGA development.
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Hack a Day
Search around the Internet and you’ll find a landfill of forum threads asking how to drive the LCD screen from a dead laptop. The answer is always that there is just no way to do it. That’s because most of them use a Low-Voltage Differential Signalling protocol that just isn’t available through the hardware used [...]
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Hack a Day
When [Mike] ran across a display on Deal Extreme with 8 seven-segment displays, 8 red/green LEDs, and 8 buttons, he knew it would find a good home in a future project. There was only one problem, though: except for an Arduino library, there was absolutely no documentation available for this display. Wanting to use this display with [...]
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Hack a Day
This game of Bomb Jack is the same as the original arcade version. The difference is that this hardware was built in an FPGA using schematics found on the Internet. We’re a little shocked by the complexity of such a project. We’ve been impressed before by the use of FPGAs to implement classic CRT vector [...]
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21:33
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SecDocs
Authors:
David Hulton Tags:
FPGA Event:
Chaos Communication Congress 23th (23C3) 2006 Abstract: This talk will go in depth into methods for breaking crypto faster using FPGAs. FPGA's are chips that have millions of gates that can be programmed and connected arbitrarily to perform any sort of task. Their inherent structure provides a perfect environment for running a variety of crypto algorithms and do so at speeds much faster than a conventional PC. A hand full of new FPGA crypto projects will be presented and will demonstrate how many algorithms can be broken much faster than people really think, and in most cases extremely inexpensively. Breaking WPA-PSK is possible with coWPAtty, but trying to do so onsite can be time consuming and boring. All that waiting around for things to be computed each and every time we want to check for dumb and default passwords. Well, we're impatient and like to know the password NOW! Josh Wright has recently added support for precomputed tables to coWPAtty -- but how do you create a good set of tables and not have it take 70 billion years? David Hulton has implemented the time consuming PBKDF2 step of WPA-PSK on FPGA hardware and optimized it to run at blazing speeds specifically for cracking WPA-PSK and generating tables with coWPAtty. What about those lusers that still use WEP? Have you only collected a few hundred interesting packets and don't want to wait till the universe implodes to crack your neighbors key? Johnycsh and David Hulton have come up with a method to offload cracking keyspaces to an FPGA and increasing the speed considerably. Lanman hashes have been broken for a long time and everyone knows it's faster to do a rainbowtable lookup than go through the whole keyspace. On many PC's it takes years to go through the entire typeable range, but on a small cluster of FPGAs, you can brute force that range faster than doing a rainbowtable lookup. The code for this will be briefly presented and Chipper v2.0 will be released with many new features. David Hulton will also discuss some of the aspects of algorithms that make them suitable for acceleration on FPGAs and the reasons why they run faster in hardware and touch on some future projects such as optimizations for attacking RSA and other difficult crypto algorithms.
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21:39
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SecDocs
Authors:
Christoph Weber Tags:
FPGA Event:
Chaos Communication Camp 2007 Abstract: Hardware developers ever envyed the software developers in the way that they can build and try something extremly fast an with no cost, minutes compared to days or weeks. Today the field of programable logic, mostly the FPGA, has reached a point where digital hardware design is as easy as writing software and with the possibility to make many iterations without rebuilding your device. I show you some examples and what is behind programable logic. In the rest of the presentation I present you an new compact board for FPGA based system development, the GECKO3. Starting with the description of programable logic I will go on to the ways how you can programm them, what modern tools can do for you and what you have to think about when you would like to start building your own CPUs, Cryptocrackers or other things that are better fittet in hardware than in software. After I gave you a basic knowledge of the field, I will talk about an new FPGA based application board, called GECKO3. The complete board, schematics, pcb files, source codes,... is opensource, so you can use it as it is or take it as a help to build your own system from scratch. It is an application board, these means that it is small and cheap enought to include it in your product, not like a typical big overloaded development board. These board was developed at the Berne School of Applied Science in Biel Switzerland, where I work currently. The GECKO3 is built around a large FPGA (in the range from 1 Mio. to 4 Mio Gates) and includes the necessary things to achive a fast and riskless start of YOUR project. Around the FPGA there is the powersupply, 32 Mbyte of NOR Flash, 2x64 Mbyte DDR SDRAM, 100 Mbit/s Ethernet and a USB 2.0 Controler. Most important for your own application is that you get over 160 digital I/O pins to connect your application specific hardware. The Board is completly configurable through the USB connection, you do not need a special cable. we wrote software to make it easy to exchange any data between your PC and the FPGA without any knowledge of USB.
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8:01
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Hack a Day
It’s fairly easy to create VGA with an FPGA using a simple R/2R DAC. As [Mike] points out, this requires a lot of IO pins, and many development boards only support 8 bit VGA. Analog VGA is being replaced with DVI-D and HDMI on many devices nowadays, so it would be nice to port projects from [...]
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6:01
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Hack a Day
[Dave] noted that in a recent poll of FPGA developers, emacs was far and away the most popular VHDL and Verilog editor. There are a few reasons for this – namely, emacs comes with packages for editing your HDL of choice. For those of us not wanting to install (and learn) the emacs operating system, [...]
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9:01
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Hack a Day
[Zach] sent in a project he’s been working on that brings hardware random number generators to common hardware you might have lying around. It’s called Whirlyfly and it turns an FPGA dev board into a hardware random number capable of outputting random bits over a USB connection at 3 Mbps. Previously, the whirlygig ran on [...]
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17:01
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Hack a Day
Here’s [FlorianH's] setup for driving a PlayStation Portable screen with an FPGA. He’s using the DE0-Nano board to do this, and the first order of business was to establish a way to connect the two. He did a great job of etching his own breakout board, which has some traces that are less than 10 [...]
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12:00
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Hack a Day
Even though NVidia and ATI have been open-source friendly for a while now, there still isn’t a true open-source graphics card. [Anton] and [Per] are trying to fix that by building his own graphics card around an FPGA. The project is called ORSoC, and it’s available on opencores.com. The guys are building the ORSoC graphics [...]
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21:40
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SecDocs
Authors:
Felix Domke Tags:
cracking FPGA Event:
Chaos Communication Congress 27th (27C3) 2010 Abstract: In 1998, the EFF built "Deep Crack", a machine designed to perform a walk over DES's 56-bit keyspace in nine days, for $250.000. With today's FPGA technology, a cost decrease of 25x can be achieved, as the copacobana project has shown. If that's still too much, two approaches should be considered: Recycling hardware and distributed computing. This talk will be about combining both approaches for the greater good. A number of projects (Copacobana, Picocomputing) have shown that with today's technology enough brute force computing power to break limited keylength ciphers (like DES) is affordable even for small companies. But what about Joe Geek at home? Recycling FPGAs is one option (nsa@home), distributed computing another (distributed.net, ...). This project combines both approaches, developing a toolchain that can be used to prototype a project on a low-end FPGA (or even in a free simulator), and then scaling up the effort across different implementations onto a large number of devices. An example client implementation uses an FPGA in a widely available consumer device to provide computing power when the device is in standby. Another approach that will be discussed in detail is how to obtain decommissioned high-end FPGA-based hardware. We will have hardware to show with a live demo!
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21:40
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SecDocs
Authors:
Felix Domke Tags:
cracking FPGA Event:
Chaos Communication Congress 27th (27C3) 2010 Abstract: In 1998, the EFF built "Deep Crack", a machine designed to perform a walk over DES's 56-bit keyspace in nine days, for $250.000. With today's FPGA technology, a cost decrease of 25x can be achieved, as the copacobana project has shown. If that's still too much, two approaches should be considered: Recycling hardware and distributed computing. This talk will be about combining both approaches for the greater good. A number of projects (Copacobana, Picocomputing) have shown that with today's technology enough brute force computing power to break limited keylength ciphers (like DES) is affordable even for small companies. But what about Joe Geek at home? Recycling FPGAs is one option (nsa@home), distributed computing another (distributed.net, ...). This project combines both approaches, developing a toolchain that can be used to prototype a project on a low-end FPGA (or even in a free simulator), and then scaling up the effort across different implementations onto a large number of devices. An example client implementation uses an FPGA in a widely available consumer device to provide computing power when the device is in standby. Another approach that will be discussed in detail is how to obtain decommissioned high-end FPGA-based hardware. We will have hardware to show with a live demo!
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21:40
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SecDocs
Authors:
Felix Domke Tags:
cracking FPGA Event:
Chaos Communication Congress 27th (27C3) 2010 Abstract: In 1998, the EFF built "Deep Crack", a machine designed to perform a walk over DES's 56-bit keyspace in nine days, for $250.000. With today's FPGA technology, a cost decrease of 25x can be achieved, as the copacobana project has shown. If that's still too much, two approaches should be considered: Recycling hardware and distributed computing. This talk will be about combining both approaches for the greater good. A number of projects (Copacobana, Picocomputing) have shown that with today's technology enough brute force computing power to break limited keylength ciphers (like DES) is affordable even for small companies. But what about Joe Geek at home? Recycling FPGAs is one option (nsa@home), distributed computing another (distributed.net, ...). This project combines both approaches, developing a toolchain that can be used to prototype a project on a low-end FPGA (or even in a free simulator), and then scaling up the effort across different implementations onto a large number of devices. An example client implementation uses an FPGA in a widely available consumer device to provide computing power when the device is in standby. Another approach that will be discussed in detail is how to obtain decommissioned high-end FPGA-based hardware. We will have hardware to show with a live demo!
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10:01
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Hack a Day
From time to time we find ourselves in the mood for some Chiptunes. You know, the music that accompanied all of the best 8-bit console games? These days there are a lot of projects that use the audio chips of yore to recreate the sounds, but you’re always faced with the issue of sourcing those [...]
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21:46
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SecDocs
Tags:
cryptography Event:
Chaos Communication Congress 28th (28C3) 2011 Abstract: A non-copyright circumventing application of the HDCP master key A man-in-the-middle attack on HDCP-secured video links is demonstrated. The attack is implemented on an embedded Linux platform, with the help of a Spartan-6 FPGA, and is capable of operating real-time on HD video links. It utilizes the HDCP master key to derive the corresponding private keys of the video source and sink through observation and computation upon the exchanged public keys. The man-in-the-middle then genlocks its raster and cipher state to the incoming video stream, enabling it to do pixel by pixel swapping of encrypted data. Since the link does no CRC or hash verification of the data, one is able to forge video using this method. Significantly, the attack enables forging of video data without decrypting original video data, so executing the attack does not constitute copyright circumvention. Therefore, this novel and commercially useful application of the HDCP master key impairs equating, in a legal sense, the master key with circumvention. Finally, the embodiment of the exploit is entirely open-source, including the hardware and the Verilog implementation of the FPGA. BACKGROUND & CONTEXT In September 2010, the HDCP master key was circulated via Pastebin. Speculation ensued around the application of the master key to create HDCP strippers, which would enable the circumvention of certain copyright control mechanisms put in place around video links. Unfortunately, this is a legally risky application, for a number of reasons, including potential conflicts with DMCA legislation that criminalizes the circumvention of copyright control mechanisms. This talk discloses a new use for the HDCP master key that side-steps some of the potential legal issues. This hack never decrypts video; without decryption, there is no circumvention, and as a result the DMCA cannot apply to this hack. Significantly, by demonstrating a bona-fide commercially significant purpose for the HDCP master key that does not circumvent an access control measure, this hack impairs the equating of trafficking or possession of the HDCP master key to circumvention and/or circumvention-related crimes. The main purpose of this hack is to enable the overlay of video content onto an HDCP encrypted stream. The simple fact that a trivial video overlay becomes an interesting topic is illustrative of the distortion of traditional rights and freedoms brought about by the DMCA. While the creation of derivative works of video through dynamic compositing and overlay (such as picture in picture) seems intuitively legal and natural in a pre-HDCP world, the introduction of HDCP made it difficult to build such in-line equipment. The putative purpose role of HDCP in the digital video ecosystem is to patch the plaintext-hole in the transmission of otherwise encrypted video from shiny disks (DVDs, BDs) to the glass (LCD, CRT). Since the implementation of video overlay would typically require manipulation of plaintext by intermediate processing elements, or at least the buffering of a plaintext frame where it can be vulnerable to readout, the creation of such devices has generally been very difficult to get past the body that controls the granting of HDCP keys, for fear that they can be hacked and/or repurposed to build an HDCP stripper. Also, while a manufacturer could implement such a feature without the controlling body's blessing, they would have to live in constant fear that their device keys would be revoked. While the applications of video overlay are numerous, the basic scenario is that while you may be enjoying content X, you would also like to be aware of content Y. To combine the two together would require a video overlay mechanism. Since video overlay mechanisms are effectively banned by the HDCP controlling organization, consumers are slaves to the video producers and distribution networks, because consumers have not been empowered to remix video at the consumption point. The specific implementation of this hack enables the overlay of a WebKit browser over any video feed; a concrete example of the capability enabled by this technology is the overlay of twitter feeds as "news crawlers" across a TV program, so that one may watch community commentary in real-time on the same screen. While some TV programs have attempted to incorporate twitter feeds into the show, the incorporation has always been on the source side, and as such users are unable to pick their hashtags. Now, with this hack, the same broadcast program (say, a political debate) can have a very different viewing experience based on which hashtag is keyed into the viewer's twitter crawler. TECHNICAL IMPLEMENTATION A Spartan-6 FPGA was used to implement a TMDS-compatible source and sink. TMDS is the signaling standard used by HDMI and DVI. The basic pipeline within the FPGA deserializes incoming video and reserializes it to the output. In this trivial mode, it is simply a signal amplifier for the video. In order to enable the overlay of a WebKit browser, an 800 MHz ARM-based Linux computer is connected to the FPGA. The Linux computer is based upon the PXA168 by Marvell, and it features 128 MB of DDR2 and a microSD card for firmware. The distribution is based upon Angstrom and it is built using OpenEmbedded with the help of buildbot. The entire build system for the Linux computer is available through a public EC2 cloud image that anyone can copy and rent from Amazon. From the Linux computer's standpoint, the FPGA emulates a parallel RGB LCD, and thus from the programming standpoint looks simply like a framebuffer at /dev/fb0. There is also a device management interface revealed through I2C that is managed using the standard Linux I2C driver. The I2C management interface handles routine status requests, such as reading the video timing and PLL state, and also handles reading out sections of snooping buffers, the significance of which will be discussed later. The FPGA also has a chroma-key feature where a magic color (240,0,240) is remapped to "transparent". The FPGA itself is bootstrapped through a programming interface where the device’s compiled bitstream is sent to the FPGA by writing to /dev/fpga. There are also IOCTLs available on /dev/fpga that enable other meta-level functions such as resetting the FPGA or querying its configuration state. In addition to passing through the TMDS signal, the FPGA also has the ability to listen to and manipulate the DDC. The DDC is an I2C link found on HDMI cables that enables the reporting of monitor capability records (EDIDs) and also is the medium upon which the key exchange happens. Therefore, being able to listen to this passively is of great importance to the hack. The FPGA implements a "shadow-RAM" which records all reads and writes to specific addresses that fall within the expected address ranges for EDID and HDCP transactions. The FPGA also implements a "squash-RAM" which is used to override bits on the I2C bus. Since I2C is an open collector standard, overriding a 1 to a 0 is trivial; but, overriding a 0 to a 1 requires an active pull-up. The hardware implements a beefy FET on the DDC to enable overriding 0's to 1's. The DDC implementation uses a highly oversampled I2C state machine. I2C itself only runs at 100 kHz, but the state machine implementation runs at 26 MHz. This allows the state machine to determine the next state of the I2C bus and decide to override or allow the transaction on-the-fly. The "squash-RAM" feature is used to override the EDID negotiation such that the video source is only informed of modes that the FPGA implementation can handle. For example, this implementation cannot handle 3D TV resolutions, so the reporting of such capabilities from the TV is squashed before it can get to the video source. This causes the source to automatically limit its content to be within the hardware capabilities of the FPGA, and to be within the resolutions that are supported by the WebKit UI. The key exchange on HDCP consists of three pieces of data being passed back and forth: the source public key (Aksv), the sink public key (Bksv), and a piece of shared state (An). The order in which these are written is well-defined. The completion of the transfer of the final byte of Aksv serves as a trigger to initialize the cipher states of the source and the sink. During this time period, each device computes the dot-product of the other device's KSV with their internal private key (which is a table of forty 56-bit numbers) and derives a shared secret, known as Km. This is basically an implementation of Blom's Scheme. In order to implement the man-in-the-middle attack, the three pieces of data are recorded, and the authentication trigger is passed from the FPGA to the Linux computer through an udev event. udev triggers a program that reads the KSVs from the snoop memory, and performs a computation upon the HDCP master key and the KSVs to derive the private keys that mirrors those found in each of the source and sink devices. In a nutshell, the computation loops through the 40x40 matrix of the HDCP master key, and based upon the KSV having a 1 at a particular bit position it sums in the corresponding 40-entry row or column of the master key to the 40-entry private key vector. The use of a row or columns depends upon if the KSV belongs to a source or a sink. Once the private keys vectors have been derived, they can be multiplied in exactly the same fashion as would be found in the source or sink to derive the shared secret, Km. This shared secret, Km, is then written into the FPGA's HDCP engine, and the cipher state is ready to go. In practice, the entire computation can happen in real-time, but some devices go faster or slower than others, so it is hard to guarantee it always completes in time, particularly with the variable interrupt latency of the udev handler. As a result, the actual link negotiation caches the value of Km from previous authentications, and the udev event primarily verifies that Km hasn't changed (note that for each given source and sink pair, Km is static and never changes, so unless users are pulling cables out and swapping them between devices, Km is essentially static). If the Km has changed, it updates the Km in the FPGA and forces a 150ms hot plug event, which re-initiates the authentication, thereby making the transaction fairly reliable yet effectively real-time. Significantly, this system as implemented is incapable of operating without having the public keys provided by both the source and the sink. This means that it cannot "create" an HDCP link: this implementation is not an operational HDCP engine on its own. Rather, it requires the user of this overlay hack to "prove" it has previously purchased a full HDCP link through evidence of valid public keys. This “proof of purchase” exhausts the proprietary rights to the link associated with first sale doctrine. Once the FPGA's HDCP cipher state is matched to the video source's cipher state, one can now selectively encrypt different pixels to replace original pixels, and the receiver will decrypt all without any error condition. This is because encryption is done on a pixel by pixel basis and the receiver does little in the way of verification. The lack of link verification is in fact quite intentional and necessary. The natural bit error rate of HD video links is atrocious; but this is acceptable, because the human eye probably won't detect bit errors even on the level of 1 in every 10,000 bits (at high error rates, users see a “sparkle” or “snow” on the screen, but largely the image is intact). Therefore, this latitude in allowing pixel-level corruption is necessary to keep consumer costs low; otherwise, much higher quality cables would be required along with FEC techniques to achieve a bit error rate that is compatible with strict cryptographic verification techniques such as full-frame hashing. The selection of which pixel to swap is done by observing the color of the overlay's video. The overlay video is not encrypted and is generated by the user, so there is no legal violation to look at the color of the overlay video. Note that other pixel-combining methods, such as alpha blending, would necessitate the decryption of video. If the overlay video matches a certain chroma key color, the incoming video is selected; otherwise, the overlay video is selected. This allows for the creation of transparent "holes" in the UI. Since the UI is rendered by a WebKit browser, chroma-key is implemented by simply setting the background color in the CSS of the UI pages to magic-pink. This makes the default state of a web page transparent, with all items rendered on top of it opaque. Note that pixel-by-pixel manipulation of the incoming video feed is done without any real buffering of the video. A TMDS pixel "lives" inside the FPGA for less than a couple dozen clock cycles: the lifetime of a pixel is simply the latency of the pipelines and the elastic buffers required to deskew wire length differences between differential pairs. This means that the overlay video from the Linux computer must be strictly available at exactly the right time, or else the user will see the overlay jitter and shake. In order to avoid such artifacts, the time resolution requirement of the pixel synchronization is stricter than the width of a pixclock period, which can be as short as dozen nanoseconds. In order to accomplish this fine-grain synchronization, a genlock mechanism was implemented where vertical retrace signals (which are unencrypted) trigger an interrupt that initiates the readout of /dev/fb0 to the FPGA. However, the interrupt jitter of a non-realtime Linux is much larger than a single pixel time, so in order to absorb this uncertainty, a dynamic genlock engine was implemented in the FPGA. An 8-line overlay video FIFO is used to provide the timing elasticity between the Linux computer and the primary video feed; and the vertical sync interrupt-to-pixel-out latency of the Linux computer is dynamically measured by the FPGA and pre-compensated. In effect, the FPGA measures how slow the Linux box's reflexes are, and requests for the frame to start coming in advance of when the data is needed. These measures, along with a few lines of FIFO, ensure pixel availability at the precise time when the pixel is needed. SUMMARY A system has been described that enables a man-in-the-middle attack upon HDCP secured links. The attack enables the overlay of video upon existing streams; an example of an application of the attack is the overlay of a personalized twitter feed over video programs. The attack relies upon the HDCP master key and a snooping mechanism implemented using an FPGA. The implementation of the attack never decrypts previously encrypted video, and it is incapable of operating without an existing, valid HDCP link. It is thus an embodiment of a bona-fide, non-infringing and commercially useful application of the HDCP master key. This embodiment impairs the equating of the HDCP master key with copyright circumvention purposes.
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21:46
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SecDocs
Tags:
cryptography Event:
Chaos Communication Congress 28th (28C3) 2011 Abstract: A non-copyright circumventing application of the HDCP master key A man-in-the-middle attack on HDCP-secured video links is demonstrated. The attack is implemented on an embedded Linux platform, with the help of a Spartan-6 FPGA, and is capable of operating real-time on HD video links. It utilizes the HDCP master key to derive the corresponding private keys of the video source and sink through observation and computation upon the exchanged public keys. The man-in-the-middle then genlocks its raster and cipher state to the incoming video stream, enabling it to do pixel by pixel swapping of encrypted data. Since the link does no CRC or hash verification of the data, one is able to forge video using this method. Significantly, the attack enables forging of video data without decrypting original video data, so executing the attack does not constitute copyright circumvention. Therefore, this novel and commercially useful application of the HDCP master key impairs equating, in a legal sense, the master key with circumvention. Finally, the embodiment of the exploit is entirely open-source, including the hardware and the Verilog implementation of the FPGA. BACKGROUND & CONTEXT In September 2010, the HDCP master key was circulated via Pastebin. Speculation ensued around the application of the master key to create HDCP strippers, which would enable the circumvention of certain copyright control mechanisms put in place around video links. Unfortunately, this is a legally risky application, for a number of reasons, including potential conflicts with DMCA legislation that criminalizes the circumvention of copyright control mechanisms. This talk discloses a new use for the HDCP master key that side-steps some of the potential legal issues. This hack never decrypts video; without decryption, there is no circumvention, and as a result the DMCA cannot apply to this hack. Significantly, by demonstrating a bona-fide commercially significant purpose for the HDCP master key that does not circumvent an access control measure, this hack impairs the equating of trafficking or possession of the HDCP master key to circumvention and/or circumvention-related crimes. The main purpose of this hack is to enable the overlay of video content onto an HDCP encrypted stream. The simple fact that a trivial video overlay becomes an interesting topic is illustrative of the distortion of traditional rights and freedoms brought about by the DMCA. While the creation of derivative works of video through dynamic compositing and overlay (such as picture in picture) seems intuitively legal and natural in a pre-HDCP world, the introduction of HDCP made it difficult to build such in-line equipment. The putative purpose role of HDCP in the digital video ecosystem is to patch the plaintext-hole in the transmission of otherwise encrypted video from shiny disks (DVDs, BDs) to the glass (LCD, CRT). Since the implementation of video overlay would typically require manipulation of plaintext by intermediate processing elements, or at least the buffering of a plaintext frame where it can be vulnerable to readout, the creation of such devices has generally been very difficult to get past the body that controls the granting of HDCP keys, for fear that they can be hacked and/or repurposed to build an HDCP stripper. Also, while a manufacturer could implement such a feature without the controlling body's blessing, they would have to live in constant fear that their device keys would be revoked. While the applications of video overlay are numerous, the basic scenario is that while you may be enjoying content X, you would also like to be aware of content Y. To combine the two together would require a video overlay mechanism. Since video overlay mechanisms are effectively banned by the HDCP controlling organization, consumers are slaves to the video producers and distribution networks, because consumers have not been empowered to remix video at the consumption point. The specific implementation of this hack enables the overlay of a WebKit browser over any video feed; a concrete example of the capability enabled by this technology is the overlay of twitter feeds as "news crawlers" across a TV program, so that one may watch community commentary in real-time on the same screen. While some TV programs have attempted to incorporate twitter feeds into the show, the incorporation has always been on the source side, and as such users are unable to pick their hashtags. Now, with this hack, the same broadcast program (say, a political debate) can have a very different viewing experience based on which hashtag is keyed into the viewer's twitter crawler. TECHNICAL IMPLEMENTATION A Spartan-6 FPGA was used to implement a TMDS-compatible source and sink. TMDS is the signaling standard used by HDMI and DVI. The basic pipeline within the FPGA deserializes incoming video and reserializes it to the output. In this trivial mode, it is simply a signal amplifier for the video. In order to enable the overlay of a WebKit browser, an 800 MHz ARM-based Linux computer is connected to the FPGA. The Linux computer is based upon the PXA168 by Marvell, and it features 128 MB of DDR2 and a microSD card for firmware. The distribution is based upon Angstrom and it is built using OpenEmbedded with the help of buildbot. The entire build system for the Linux computer is available through a public EC2 cloud image that anyone can copy and rent from Amazon. From the Linux computer's standpoint, the FPGA emulates a parallel RGB LCD, and thus from the programming standpoint looks simply like a framebuffer at /dev/fb0. There is also a device management interface revealed through I2C that is managed using the standard Linux I2C driver. The I2C management interface handles routine status requests, such as reading the video timing and PLL state, and also handles reading out sections of snooping buffers, the significance of which will be discussed later. The FPGA also has a chroma-key feature where a magic color (240,0,240) is remapped to "transparent". The FPGA itself is bootstrapped through a programming interface where the device’s compiled bitstream is sent to the FPGA by writing to /dev/fpga. There are also IOCTLs available on /dev/fpga that enable other meta-level functions such as resetting the FPGA or querying its configuration state. In addition to passing through the TMDS signal, the FPGA also has the ability to listen to and manipulate the DDC. The DDC is an I2C link found on HDMI cables that enables the reporting of monitor capability records (EDIDs) and also is the medium upon which the key exchange happens. Therefore, being able to listen to this passively is of great importance to the hack. The FPGA implements a "shadow-RAM" which records all reads and writes to specific addresses that fall within the expected address ranges for EDID and HDCP transactions. The FPGA also implements a "squash-RAM" which is used to override bits on the I2C bus. Since I2C is an open collector standard, overriding a 1 to a 0 is trivial; but, overriding a 0 to a 1 requires an active pull-up. The hardware implements a beefy FET on the DDC to enable overriding 0's to 1's. The DDC implementation uses a highly oversampled I2C state machine. I2C itself only runs at 100 kHz, but the state machine implementation runs at 26 MHz. This allows the state machine to determine the next state of the I2C bus and decide to override or allow the transaction on-the-fly. The "squash-RAM" feature is used to override the EDID negotiation such that the video source is only informed of modes that the FPGA implementation can handle. For example, this implementation cannot handle 3D TV resolutions, so the reporting of such capabilities from the TV is squashed before it can get to the video source. This causes the source to automatically limit its content to be within the hardware capabilities of the FPGA, and to be within the resolutions that are supported by the WebKit UI. The key exchange on HDCP consists of three pieces of data being passed back and forth: the source public key (Aksv), the sink public key (Bksv), and a piece of shared state (An). The order in which these are written is well-defined. The completion of the transfer of the final byte of Aksv serves as a trigger to initialize the cipher states of the source and the sink. During this time period, each device computes the dot-product of the other device's KSV with their internal private key (which is a table of forty 56-bit numbers) and derives a shared secret, known as Km. This is basically an implementation of Blom's Scheme. In order to implement the man-in-the-middle attack, the three pieces of data are recorded, and the authentication trigger is passed from the FPGA to the Linux computer through an udev event. udev triggers a program that reads the KSVs from the snoop memory, and performs a computation upon the HDCP master key and the KSVs to derive the private keys that mirrors those found in each of the source and sink devices. In a nutshell, the computation loops through the 40x40 matrix of the HDCP master key, and based upon the KSV having a 1 at a particular bit position it sums in the corresponding 40-entry row or column of the master key to the 40-entry private key vector. The use of a row or columns depends upon if the KSV belongs to a source or a sink. Once the private keys vectors have been derived, they can be multiplied in exactly the same fashion as would be found in the source or sink to derive the shared secret, Km. This shared secret, Km, is then written into the FPGA's HDCP engine, and the cipher state is ready to go. In practice, the entire computation can happen in real-time, but some devices go faster or slower than others, so it is hard to guarantee it always completes in time, particularly with the variable interrupt latency of the udev handler. As a result, the actual link negotiation caches the value of Km from previous authentications, and the udev event primarily verifies that Km hasn't changed (note that for each given source and sink pair, Km is static and never changes, so unless users are pulling cables out and swapping them between devices, Km is essentially static). If the Km has changed, it updates the Km in the FPGA and forces a 150ms hot plug event, which re-initiates the authentication, thereby making the transaction fairly reliable yet effectively real-time. Significantly, this system as implemented is incapable of operating without having the public keys provided by both the source and the sink. This means that it cannot "create" an HDCP link: this implementation is not an operational HDCP engine on its own. Rather, it requires the user of this overlay hack to "prove" it has previously purchased a full HDCP link through evidence of valid public keys. This “proof of purchase” exhausts the proprietary rights to the link associated with first sale doctrine. Once the FPGA's HDCP cipher state is matched to the video source's cipher state, one can now selectively encrypt different pixels to replace original pixels, and the receiver will decrypt all without any error condition. This is because encryption is done on a pixel by pixel basis and the receiver does little in the way of verification. The lack of link verification is in fact quite intentional and necessary. The natural bit error rate of HD video links is atrocious; but this is acceptable, because the human eye probably won't detect bit errors even on the level of 1 in every 10,000 bits (at high error rates, users see a “sparkle” or “snow” on the screen, but largely the image is intact). Therefore, this latitude in allowing pixel-level corruption is necessary to keep consumer costs low; otherwise, much higher quality cables would be required along with FEC techniques to achieve a bit error rate that is compatible with strict cryptographic verification techniques such as full-frame hashing. The selection of which pixel to swap is done by observing the color of the overlay's video. The overlay video is not encrypted and is generated by the user, so there is no legal violation to look at the color of the overlay video. Note that other pixel-combining methods, such as alpha blending, would necessitate the decryption of video. If the overlay video matches a certain chroma key color, the incoming video is selected; otherwise, the overlay video is selected. This allows for the creation of transparent "holes" in the UI. Since the UI is rendered by a WebKit browser, chroma-key is implemented by simply setting the background color in the CSS of the UI pages to magic-pink. This makes the default state of a web page transparent, with all items rendered on top of it opaque. Note that pixel-by-pixel manipulation of the incoming video feed is done without any real buffering of the video. A TMDS pixel "lives" inside the FPGA for less than a couple dozen clock cycles: the lifetime of a pixel is simply the latency of the pipelines and the elastic buffers required to deskew wire length differences between differential pairs. This means that the overlay video from the Linux computer must be strictly available at exactly the right time, or else the user will see the overlay jitter and shake. In order to avoid such artifacts, the time resolution requirement of the pixel synchronization is stricter than the width of a pixclock period, which can be as short as dozen nanoseconds. In order to accomplish this fine-grain synchronization, a genlock mechanism was implemented where vertical retrace signals (which are unencrypted) trigger an interrupt that initiates the readout of /dev/fb0 to the FPGA. However, the interrupt jitter of a non-realtime Linux is much larger than a single pixel time, so in order to absorb this uncertainty, a dynamic genlock engine was implemented in the FPGA. An 8-line overlay video FIFO is used to provide the timing elasticity between the Linux computer and the primary video feed; and the vertical sync interrupt-to-pixel-out latency of the Linux computer is dynamically measured by the FPGA and pre-compensated. In effect, the FPGA measures how slow the Linux box's reflexes are, and requests for the frame to start coming in advance of when the data is needed. These measures, along with a few lines of FIFO, ensure pixel availability at the precise time when the pixel is needed. SUMMARY A system has been described that enables a man-in-the-middle attack upon HDCP secured links. The attack enables the overlay of video upon existing streams; an example of an application of the attack is the overlay of a personalized twitter feed over video programs. The attack relies upon the HDCP master key and a snooping mechanism implemented using an FPGA. The implementation of the attack never decrypts previously encrypted video, and it is incapable of operating without an existing, valid HDCP link. It is thus an embodiment of a bona-fide, non-infringing and commercially useful application of the HDCP master key. This embodiment impairs the equating of the HDCP master key with copyright circumvention purposes.
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21:46
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SecDocs
Tags:
cryptography Event:
Chaos Communication Congress 28th (28C3) 2011 Abstract: A non-copyright circumventing application of the HDCP master key A man-in-the-middle attack on HDCP-secured video links is demonstrated. The attack is implemented on an embedded Linux platform, with the help of a Spartan-6 FPGA, and is capable of operating real-time on HD video links. It utilizes the HDCP master key to derive the corresponding private keys of the video source and sink through observation and computation upon the exchanged public keys. The man-in-the-middle then genlocks its raster and cipher state to the incoming video stream, enabling it to do pixel by pixel swapping of encrypted data. Since the link does no CRC or hash verification of the data, one is able to forge video using this method. Significantly, the attack enables forging of video data without decrypting original video data, so executing the attack does not constitute copyright circumvention. Therefore, this novel and commercially useful application of the HDCP master key impairs equating, in a legal sense, the master key with circumvention. Finally, the embodiment of the exploit is entirely open-source, including the hardware and the Verilog implementation of the FPGA. BACKGROUND & CONTEXT In September 2010, the HDCP master key was circulated via Pastebin. Speculation ensued around the application of the master key to create HDCP strippers, which would enable the circumvention of certain copyright control mechanisms put in place around video links. Unfortunately, this is a legally risky application, for a number of reasons, including potential conflicts with DMCA legislation that criminalizes the circumvention of copyright control mechanisms. This talk discloses a new use for the HDCP master key that side-steps some of the potential legal issues. This hack never decrypts video; without decryption, there is no circumvention, and as a result the DMCA cannot apply to this hack. Significantly, by demonstrating a bona-fide commercially significant purpose for the HDCP master key that does not circumvent an access control measure, this hack impairs the equating of trafficking or possession of the HDCP master key to circumvention and/or circumvention-related crimes. The main purpose of this hack is to enable the overlay of video content onto an HDCP encrypted stream. The simple fact that a trivial video overlay becomes an interesting topic is illustrative of the distortion of traditional rights and freedoms brought about by the DMCA. While the creation of derivative works of video through dynamic compositing and overlay (such as picture in picture) seems intuitively legal and natural in a pre-HDCP world, the introduction of HDCP made it difficult to build such in-line equipment. The putative purpose role of HDCP in the digital video ecosystem is to patch the plaintext-hole in the transmission of otherwise encrypted video from shiny disks (DVDs, BDs) to the glass (LCD, CRT). Since the implementation of video overlay would typically require manipulation of plaintext by intermediate processing elements, or at least the buffering of a plaintext frame where it can be vulnerable to readout, the creation of such devices has generally been very difficult to get past the body that controls the granting of HDCP keys, for fear that they can be hacked and/or repurposed to build an HDCP stripper. Also, while a manufacturer could implement such a feature without the controlling body's blessing, they would have to live in constant fear that their device keys would be revoked. While the applications of video overlay are numerous, the basic scenario is that while you may be enjoying content X, you would also like to be aware of content Y. To combine the two together would require a video overlay mechanism. Since video overlay mechanisms are effectively banned by the HDCP controlling organization, consumers are slaves to the video producers and distribution networks, because consumers have not been empowered to remix video at the consumption point. The specific implementation of this hack enables the overlay of a WebKit browser over any video feed; a concrete example of the capability enabled by this technology is the overlay of twitter feeds as "news crawlers" across a TV program, so that one may watch community commentary in real-time on the same screen. While some TV programs have attempted to incorporate twitter feeds into the show, the incorporation has always been on the source side, and as such users are unable to pick their hashtags. Now, with this hack, the same broadcast program (say, a political debate) can have a very different viewing experience based on which hashtag is keyed into the viewer's twitter crawler. TECHNICAL IMPLEMENTATION A Spartan-6 FPGA was used to implement a TMDS-compatible source and sink. TMDS is the signaling standard used by HDMI and DVI. The basic pipeline within the FPGA deserializes incoming video and reserializes it to the output. In this trivial mode, it is simply a signal amplifier for the video. In order to enable the overlay of a WebKit browser, an 800 MHz ARM-based Linux computer is connected to the FPGA. The Linux computer is based upon the PXA168 by Marvell, and it features 128 MB of DDR2 and a microSD card for firmware. The distribution is based upon Angstrom and it is built using OpenEmbedded with the help of buildbot. The entire build system for the Linux computer is available through a public EC2 cloud image that anyone can copy and rent from Amazon. From the Linux computer's standpoint, the FPGA emulates a parallel RGB LCD, and thus from the programming standpoint looks simply like a framebuffer at /dev/fb0. There is also a device management interface revealed through I2C that is managed using the standard Linux I2C driver. The I2C management interface handles routine status requests, such as reading the video timing and PLL state, and also handles reading out sections of snooping buffers, the significance of which will be discussed later. The FPGA also has a chroma-key feature where a magic color (240,0,240) is remapped to "transparent". The FPGA itself is bootstrapped through a programming interface where the device’s compiled bitstream is sent to the FPGA by writing to /dev/fpga. There are also IOCTLs available on /dev/fpga that enable other meta-level functions such as resetting the FPGA or querying its configuration state. In addition to passing through the TMDS signal, the FPGA also has the ability to listen to and manipulate the DDC. The DDC is an I2C link found on HDMI cables that enables the reporting of monitor capability records (EDIDs) and also is the medium upon which the key exchange happens. Therefore, being able to listen to this passively is of great importance to the hack. The FPGA implements a "shadow-RAM" which records all reads and writes to specific addresses that fall within the expected address ranges for EDID and HDCP transactions. The FPGA also implements a "squash-RAM" which is used to override bits on the I2C bus. Since I2C is an open collector standard, overriding a 1 to a 0 is trivial; but, overriding a 0 to a 1 requires an active pull-up. The hardware implements a beefy FET on the DDC to enable overriding 0's to 1's. The DDC implementation uses a highly oversampled I2C state machine. I2C itself only runs at 100 kHz, but the state machine implementation runs at 26 MHz. This allows the state machine to determine the next state of the I2C bus and decide to override or allow the transaction on-the-fly. The "squash-RAM" feature is used to override the EDID negotiation such that the video source is only informed of modes that the FPGA implementation can handle. For example, this implementation cannot handle 3D TV resolutions, so the reporting of such capabilities from the TV is squashed before it can get to the video source. This causes the source to automatically limit its content to be within the hardware capabilities of the FPGA, and to be within the resolutions that are supported by the WebKit UI. The key exchange on HDCP consists of three pieces of data being passed back and forth: the source public key (Aksv), the sink public key (Bksv), and a piece of shared state (An). The order in which these are written is well-defined. The completion of the transfer of the final byte of Aksv serves as a trigger to initialize the cipher states of the source and the sink. During this time period, each device computes the dot-product of the other device's KSV with their internal private key (which is a table of forty 56-bit numbers) and derives a shared secret, known as Km. This is basically an implementation of Blom's Scheme. In order to implement the man-in-the-middle attack, the three pieces of data are recorded, and the authentication trigger is passed from the FPGA to the Linux computer through an udev event. udev triggers a program that reads the KSVs from the snoop memory, and performs a computation upon the HDCP master key and the KSVs to derive the private keys that mirrors those found in each of the source and sink devices. In a nutshell, the computation loops through the 40x40 matrix of the HDCP master key, and based upon the KSV having a 1 at a particular bit position it sums in the corresponding 40-entry row or column of the master key to the 40-entry private key vector. The use of a row or columns depends upon if the KSV belongs to a source or a sink. Once the private keys vectors have been derived, they can be multiplied in exactly the same fashion as would be found in the source or sink to derive the shared secret, Km. This shared secret, Km, is then written into the FPGA's HDCP engine, and the cipher state is ready to go. In practice, the entire computation can happen in real-time, but some devices go faster or slower than others, so it is hard to guarantee it always completes in time, particularly with the variable interrupt latency of the udev handler. As a result, the actual link negotiation caches the value of Km from previous authentications, and the udev event primarily verifies that Km hasn't changed (note that for each given source and sink pair, Km is static and never changes, so unless users are pulling cables out and swapping them between devices, Km is essentially static). If the Km has changed, it updates the Km in the FPGA and forces a 150ms hot plug event, which re-initiates the authentication, thereby making the transaction fairly reliable yet effectively real-time. Significantly, this system as implemented is incapable of operating without having the public keys provided by both the source and the sink. This means that it cannot "create" an HDCP link: this implementation is not an operational HDCP engine on its own. Rather, it requires the user of this overlay hack to "prove" it has previously purchased a full HDCP link through evidence of valid public keys. This “proof of purchase” exhausts the proprietary rights to the link associated with first sale doctrine. Once the FPGA's HDCP cipher state is matched to the video source's cipher state, one can now selectively encrypt different pixels to replace original pixels, and the receiver will decrypt all without any error condition. This is because encryption is done on a pixel by pixel basis and the receiver does little in the way of verification. The lack of link verification is in fact quite intentional and necessary. The natural bit error rate of HD video links is atrocious; but this is acceptable, because the human eye probably won't detect bit errors even on the level of 1 in every 10,000 bits (at high error rates, users see a “sparkle” or “snow” on the screen, but largely the image is intact). Therefore, this latitude in allowing pixel-level corruption is necessary to keep consumer costs low; otherwise, much higher quality cables would be required along with FEC techniques to achieve a bit error rate that is compatible with strict cryptographic verification techniques such as full-frame hashing. The selection of which pixel to swap is done by observing the color of the overlay's video. The overlay video is not encrypted and is generated by the user, so there is no legal violation to look at the color of the overlay video. Note that other pixel-combining methods, such as alpha blending, would necessitate the decryption of video. If the overlay video matches a certain chroma key color, the incoming video is selected; otherwise, the overlay video is selected. This allows for the creation of transparent "holes" in the UI. Since the UI is rendered by a WebKit browser, chroma-key is implemented by simply setting the background color in the CSS of the UI pages to magic-pink. This makes the default state of a web page transparent, with all items rendered on top of it opaque. Note that pixel-by-pixel manipulation of the incoming video feed is done without any real buffering of the video. A TMDS pixel "lives" inside the FPGA for less than a couple dozen clock cycles: the lifetime of a pixel is simply the latency of the pipelines and the elastic buffers required to deskew wire length differences between differential pairs. This means that the overlay video from the Linux computer must be strictly available at exactly the right time, or else the user will see the overlay jitter and shake. In order to avoid such artifacts, the time resolution requirement of the pixel synchronization is stricter than the width of a pixclock period, which can be as short as dozen nanoseconds. In order to accomplish this fine-grain synchronization, a genlock mechanism was implemented where vertical retrace signals (which are unencrypted) trigger an interrupt that initiates the readout of /dev/fb0 to the FPGA. However, the interrupt jitter of a non-realtime Linux is much larger than a single pixel time, so in order to absorb this uncertainty, a dynamic genlock engine was implemented in the FPGA. An 8-line overlay video FIFO is used to provide the timing elasticity between the Linux computer and the primary video feed; and the vertical sync interrupt-to-pixel-out latency of the Linux computer is dynamically measured by the FPGA and pre-compensated. In effect, the FPGA measures how slow the Linux box's reflexes are, and requests for the frame to start coming in advance of when the data is needed. These measures, along with a few lines of FIFO, ensure pixel availability at the precise time when the pixel is needed. SUMMARY A system has been described that enables a man-in-the-middle attack upon HDCP secured links. The attack enables the overlay of video upon existing streams; an example of an application of the attack is the overlay of a personalized twitter feed over video programs. The attack relies upon the HDCP master key and a snooping mechanism implemented using an FPGA. The implementation of the attack never decrypts previously encrypted video, and it is incapable of operating without an existing, valid HDCP link. It is thus an embodiment of a bona-fide, non-infringing and commercially useful application of the HDCP master key. This embodiment impairs the equating of the HDCP master key with copyright circumvention purposes.
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12:01
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Hack a Day
Building an audio player is a fun project. It used to be quite a task to do so, but these days the MP3 decoder chips are full-featured which means that if you know how to talk to other chips with a microcontroller you’ve got all the skills needed to pull off the project. But that [...]
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14:01
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Hack a Day
Here is [Voelker] showing off his FPGA-based camera hardware. He picked up an ov7670 camera on eBay for about $10 and set to work pulling pixels and processing the images. He’s now able to grab thirty frames per second and push them to his own Java display application. He’s using the Papilio board and if you [...]
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9:01
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Hack a Day
[Cesar] recently got a PSP display up and running with his FPGA development board. That’s a nice project, but what we really like is that he set aside a lot of time to show how it’s done every step of the way. This isn’t just a tutorial on that particular screen, but an overview of [...]
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9:01
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Hack a Day
We’re really not supposed to start a feature like this; but this hack is awesome. It’s a game of Snake implemented by an FPGA dev board. It uses a 16×16 LED matrix as the display and an SNES controller for input. So far it sounds like a very normal version of the game. But as [...]
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7:01
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Hack a Day
[Joe] and [Evan] wanted to have some fun with their FPGA course at Cornell. When faced with what to do at the beginning of the semester, they figured additive synthesis was a worthy pursuit. They ended up building the Ocarina of Time for their final project. The guys started by recording a real ocarina and [...]
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14:26
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Hack a Day
[Andrew] is trying to buckle down and hammer out his PhD project but was surprised by the sorry state of the configuration options for his FPGA/ARM dev board. Using JTAG was painfully slow, so he studied the datasheet to see if there was another way. It turns out the Xilinx FPGA he’s using does have [...]
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11:01
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Hack a Day
[Thomas’] love affair with Commodore computers spans well over 30 years, and not too long ago he decided to recreate one of his favorite Commodore offerings, the PET. As we have seen with similar undertakings, this sort of project is no easy task, but [Thomas] seems to be making his way along nicely. Using a [...]
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16:01
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Hack a Day
[Mike] has been filling up a rather intense wiki entry outlining how to run uClinux on a DE0-nano FPGA board. This is an inexpensive dev board that will run you somewhere between $80 and $100. Right off the bat he goes into a hefty list of the reasons that this is a foolish activity. To name [...]
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14:05
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Hack a Day
[Steve] over at Big Mess O’ Wires has never been so happy to see the “Sad Mac” icon. A little over a month ago, he decided to take on the task of building his own Mac clone using modern technology. Not to be confused with Mac emulation on modern hardware, he is attempting to build [...]
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11:11
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Hack a Day
[Mike Field] took what he had learned with a few past projects and combined them to make this FPGA-based SPDIF audio pass-through. In order to get the SPDIF signal ready for the FPGA he needed a few components to use for level conversion. Once everything was connected he used a first in first out (FIFO) buffer [...]
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8:01
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Hack a Day
[fpgaminer], [li_gangyi], and [newMeat1] have been working together for the last few months to build an FPGA bitcoin miner that blows GPU mining rigs out of the water in terms of power efficiency. The board requires only 6.8 watts for 100 Mhashes/second, but [li_gangyi]‘s blog says the team expects to hit 150-200 Mhashes with some [...]
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14:05
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Hack a Day
[dgcx] has been working on reimplementing a PDP-10/x on an FPGA for the last 2 and a half years. This surprised us because we’re only hearing about this project now. After designing three versions, [dgcx] eventually ended up with a one-FPGA implementation of a PDP-10 and an awesome PDF writeup. Although PDP-10 emulators do exist, [...]
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4:06
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Hack a Day
[Bruce Land] is a professor at Cornell University who was looking for a way to quickly solve chemical kinetic systems. He had used MATLAB but longed for a faster method. His upgrade achieves a 100 times speed increase by using an FPGA as a parallel stochastic solver. It works by generating 100 pseudo-random 16-bit numbers [...]
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11:01
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Hack a Day
[ Jack Gassett] is working on an FPGA shield for the Arduino. At first the idea of this expansion board seemed a little silly. But [Jack] mentions that the FPGA board can be quite useful for adding higher-order electronic complexity like HDMI capabilities to an Arduino. We’re not totally sold on the idea, but he’s not [...]
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11:01
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Hack a Day
[Mike Field] just finished implementing SPDIF generation on an FPGA. SPDIF is an industry standard for transmitting digital audio signals; the acronym stands for Sony/Philips Digital Interconnect Format. It’s been around for more than a decade and since it’s found on most home-audio equipment, building an SPDIF output into your projects may be quite a desirable feature. [...]
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9:00
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Hack a Day
A week or so ago we featured an FPGA MIDI interface. Since then the builder has gone crazy with his FPGA and revised his code to include polyphony and PWM output, and posted a polyphony demo. In our previous coverage of the build, the synth was monophonic, and the MIDI implementation was pretty shaky. After [...]
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7:32
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Hack a Day
Hacking and digital music seem to be very much related arts. This very well built hack goes through the process of creating a MIDI synthesizer using a field programmable gate array (FPGA) and several other components. A laptop is used as the MIDI interface which runs through a filter and then to the FPGA. This [...]
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5:07
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Hack a Day
[Mike Field] has always been interested in the Mandelbrot Set since he first read about it back in the ‘80s. Having coded it on a Commodore VIC20 back int he day, he always returned to the Mandelbrot set when he wanted to try out some new programming technology. He wanted to delve deeper into the [...]
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10:48
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Hack a Day
[devb] has been playing around with XESS FPGA boards for ages, and as long as he can remember, they have had built-in VGA interfaces. His newest acquisition, a XuLA FPGA board, doesn’t have any external parts or ports aside from a USB connector. He needed to get video output from the board, so he decided [...]
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10:01
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Hack a Day
[Gregory] wrote in to share his most recent project, an FPGA clone of the PC Engine/Turbografx 16 console. You may remember him from last year, when we talked about his SEGA Genesis FPGA clone. He just couldn’t leave well enough alone, and decided to resurrect yet another 16-bit machine in FPGA form. He has been [...]
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5:04
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Hack a Day
[Matt's] finishing up his computer science degree. As part of a class assignment he programmed his own sequencer which runs on a Cyclone-II FPGA development board. We’ve embedded a video below the fold that shows you what it can do. The buttons and LEDs offered on the board actually allowed him to create a nice [...]
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6:11
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Hack a Day
Okay, now we’re beginning to feel a bit like [Alice]. This tutorial shows you how to simulate VHDL code. This code is intended to run on an FPGA and includes a software-only version of the AVR 8-bit microcontroller core. Essentially, you’ll simulate VHDL code that simulates AVR hardware. Wrap your mind around that! The code [...]
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4:05
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Hack a Day
Gameduino is an FPGA based sound and graphics adapter for microcontrollers. Laid out as an Arduino shield, all it really takes is a microcontroller with SPI and some code to send commands to the board which lets you toggle registers, handle memory, and drawing functions. Once the data gets there, it is greeted by a [...]
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12:00
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Hack a Day
[James Bowman] of the Willow Garage published a paper on his J1 CPU core for field-programmable gate arrays. This was originally developed and used for the Ethernet cameras on the PR2 (you know, that incredibly expensive beer delivery system?) robot. It uses a 16-bit von Neumann architecture and lacks several processor features you’d expect a [...]
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13:00
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Hack a Day
[Greg] managed to clone a SEGA Genesis using a field programmable gate array. He used a Terasic/Altera DE1 board, which will set you back about $160, during development. The onboard push buttons are currently used as the controller with VGA for the display. Who knows, maybe there’s enough programming space left to drive a PSP [...]
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9:04
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Hack a Day
If you think that Arduinos are overkill in most projects we can do one better for you. [Jack Gassett] has a virtual Arduino running on a Field Programmable Gate Array. We checked in with [Jack] back in November to see his work with the AVR8 Soft Processor, an FPGA version of an AVR chip. Because [...]
